Title
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
Abstract
The limited size and power budgets of space-bound systems often contradict the requirements for reliable circuit operation within high-radiation environments. In this paper, we propose the smallest solution for soft-error tolerant embedded memory yet to be presented. The proposed complementary dual-modular redundancy (CDMR) memory is based on a four-transistor dynamic memory core that internally stores complementary data values to provide an inherent per-bit error detection capability. By adding simple, low-overhead parity, an error-correction capability is added to the memory architecture for robust soft-error protection. The proposed memory was implemented in a 65-nm CMOS technology, displaying as much as a 3.5×1 smaller silicon footprint than other radiation-hardened bitcells. In addition, the CDMR memory consumes between 48% and 87% less standby power than other considered solutions across the entire operating region.
Year
DOI
Venue
2017
10.1109/TVLSI.2016.2603923
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
Redundancy,Memory management,Transistors,SRAM cells,Inverters,Power demand
Sense amplifier,Registered memory,Semiconductor memory,Interleaved memory,Computer science,Real-time computing,Electronic engineering,Memory management,Computer memory,Memory architecture,Memory refresh
Journal
Volume
Issue
ISSN
25
2
1063-8210
Citations 
PageRank 
References 
1
0.36
9
Authors
3
Name
Order
Citations
PageRank
Robert Giterman1409.55
lior atias291.36
Adam Teman312919.12