Name
Abstract | ||
|---|---|---|
Speed, portability and correctness have traditionally been the main requirements for dynamic binary translation (DBT) systems. Given the increasing availability of multi-core machines as both emulation guests and hosts, scalability has emerged as an additional design objective. It has however been an elusive goal for two reasons: contention on common data structures such as the translation cache is difficult to avoid without hurting performance, and instruction set architecture (ISA) disparities between guest and host (such as mismatches in the memory consistency model and the semantics of atomic operations) can compromise correctness. In this paper we address these challenges in a simple and memory-efficient way, demonstrating a multi-threaded DBT-based emulator that scales in an architecture-independent manner. Furthermore, we explore the trade-offs that exist when emulating atomic operations across ISAs, and present a novel approach for correct and scalable emulation of load-locked/store-conditional instructions based on hardware transactional memory (HTM). By adding around 1000 lines of code to QEMU, we demonstrate the scalability of both user-mode and full-system emulation on a 64-core x86_64 host running x86_64 guest code, and a 12-core, 96-thread POWER8 host running x86_64 and Aarch64 guest code. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/CGO.2017.7863741 | CGO |
Keywords | Field | DocType |
Dynamic Binary Translation, Scalability | Instruction set,Computer science,Cache,Parallel computing,Correctness,Real-time computing,Transactional memory,Emulation,Binary translation,Operating system,Scalability,Hardware emulation | Conference |
ISSN | ISBN | Citations |
2164-2397 | 978-1-5090-4932-5 | 1 |
PageRank | References | Authors |
0.35 | 22 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Emilio G. Cota | 1 | 53 | 4.10 |
| Paolo Bonzini | 2 | 1 | 0.35 |
| Alex Bennée | 3 | 1 | 0.35 |
| L. P. Carloni | 4 | 61 | 9.98 |