Paper Info
Title
Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA.
Abstract
Assessment of power consumption is very important for an efficient digital integrated circuit design. Dynamic power in digital programmable CMOS-based processors depends on the switching activity. Specifically in its subcomponents like FIR filter, power consumption can be directly related to the node switching activity. Minimization of power consumption can be done by reducing the transitions or dissimilarities in filter coefficients. Evolutionary algorithms (EAs) have been found to be very effective for optimized FIR filter design because of nonlinear, nondifferentiable, multimodal and nonconvex nature of the associated optimization problem. However, all the existing evolutionary optimization-based design techniques aim at meeting the frequency domain specifications without concentrating on minimizing power consumption. In the present work, a novel EA, i.e., hybrid artificial bee colony algorithm, has been proposed and further applied for FIR filter design. The filter design task aims at satisfying the dual objectives of meeting the desired frequency domain specifications and power minimization.
Year
DOI
Venue
2017
10.1007/s00034-016-0297-4
CSSP
Keywords
Field
DocType
FIR filters, Evolutionary optimization, Artificial bee colony, Power minimization, FPGA
Frequency domain,Artificial bee colony algorithm,Mathematical optimization,Evolutionary algorithm,Field-programmable gate array,Electronic engineering,Dynamic demand,Finite impulse response,Optimization problem,Mathematics,Filter design
Journal
Volume
Issue
ISSN
36
1
1531-5878
Citations 
PageRank 
References 
4
0.45
20
Authors
3
Name
Order
Citations
PageRank
Atul Kumar Dwivedi1141.33
Subhojit Ghosh2249.71
Narendra D. Londhe39813.85