Name
Abstract | ||
|---|---|---|
This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC'02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1007/s10836-016-5638-5 | J. Electronic Testing |
Keywords | Field | DocType |
Test plan,Test schedule,Test cost,Power constraint,Stacked integrated circuit,JTAG,IEEE 1149.1,Boundary scan | Boundary scan,Simulated annealing,Automatic test pattern generation,Test plan,Computer science,Real-time computing,Electronic engineering,Electronic circuit,Test compression,Integrated circuit,Reliability engineering,Computation | Journal |
Volume | Issue | ISSN |
33 | 1 | 0923-8174 |
Citations | PageRank | References |
0 | 0.34 | 18 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Breeta SenGupta | 1 | 0 | 1.01 |
| Dimitar Nikolov | 2 | 2 | 2.06 |
| Urban Ingelsson | 3 | 107 | 9.98 |
| Erik G. Larsson | 4 | 10189 | 605.81 |