Title
Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA.
Abstract
The Viterbi algorithm is commonly applied to a number of sensitive usage models including decoding convolutional codes used in communications such as satellite communication, cellular relay, and wireless local area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this paper, efficient error detection schemes for architectures based on low-l...
Year
DOI
Venue
2017
10.1109/TCSI.2016.2610187
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Field
DocType
Viterbi algorithm,Decoding,Computer architecture,Adders,Reliability,Measurement,Circuit faults
Convolutional code,Soft output Viterbi algorithm,Computer science,Field-programmable gate array,Error detection and correction,Application-specific integrated circuit,Electronic engineering,Gate array,Latency (engineering),Viterbi algorithm
Journal
Volume
Issue
ISSN
64
1
1549-8328
Citations 
PageRank 
References 
2
0.40
19
Authors
3
Name
Order
Citations
PageRank
Mehran Mozaffari Kermani1221.76
vineeta singh222.76
Reza Azarderakhsh338945.65