Name
Abstract | ||
|---|---|---|
NAND flash memories achieve very high densities through a series connection of all cells in a bitline. In current memories, each wordline is read independently by biasing all the other cells to act as pass transistors and sensing all the bitlines in parallel. This brief proposes a new method that reads multiple wordlines simultaneously and returns a combination of their stored information. This mu... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCSII.2016.2551556 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Threshold voltage,Programming,Logic gates,Transistors,Interference,Computer architecture,Sensors | Logic gate,Computer science,Electronic engineering,NAND gate,NAND logic,Interference (wave propagation),Decoding methods,Series and parallel circuits,Transistor,Computer hardware,Speedup | Journal |
Volume | Issue | ISSN |
64 | 1 | 1549-7747 |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tianqiong Luo | 1 | 3 | 1.76 |
| Borja Peleato | 2 | 4095 | 142.71 |