Name
Abstract | ||
|---|---|---|
The zero/low intermediate frequency (IF) receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of a superheterodyne RX that attempts to avoid such issues. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based bandpass filters sampled at $4\\times $ of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4–2.9 GHz with a noise figure of 2.9–4 dB. It is implemented in 65-nm CMOS and consumes 48–79 mW. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2016.2598857 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
Mixers,Band-pass filters,Receivers,Radio frequency,RF signals,Switches,Time-domain analysis | Flicker noise,Image response,Intermediate frequency,Computer science,Operational transconductance amplifier,Noise figure,Electronic engineering,Direct-conversion receiver,Electrical engineering,Local oscillator,Superheterodyne receiver | Journal |
Volume | Issue | ISSN |
25 | 2 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 27 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| massoud tohidian | 1 | 17 | 1.93 |
| Iman Madadi | 2 | 41 | 4.30 |
| Robert Bogdan Staszewski | 3 | 536 | 93.76 |