Name
Abstract | ||
|---|---|---|
The Ultra-DIMM constituted by DRAM and Flash memory is a promising solution used to tackle the challenges existing in traditional DRAM in terms of energy consuming and scalability. In this hybrid memory system, DRAM is used as the data buffer of Flash memory due to the performance and endurance gaps between main memory and Flash. However, the inconsistency of access granularity between the main memory and Flash makes the DRAM-based buffer complex. On the one hand, the basic access unit of Flash is page. However, buffering pages of Flash in DRAM without distinguishing the hot cache lines from cold cache lines within each page leads to a waste of cache capacity. On the other hand, general-purpose replacement schemes focus on high hit rate and do not consider the peculiarities of Flash, thus leads to performance and lifespan overhead. In this paper, we propose TBuffer, an additional buffer in DRAM enhanced by history-aware identification and LazyFlush. History-aware identification can increase hit rate by evicting cold cache lines and keeping more hot cache lines in DRAM, while LazyFlush can further improve performance and lifespan by delaying flushing dirty objects and reducing writes to Flash. We evaluate the TBuffer via trace-driven simulations. Experimental results have shown that it outperforms other existing schemes, increases hit rate by up to 12%, reduces the access latency by a factor of up to 50.8% with an average of 19.7%, and achieves 16.6% lifespan improvement on average. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/HPCC-SmartCity-DSS.2016.0048 | 2016 IEEE 18th International Conference on High Performance Computing and Communications; IEEE 14th International Conference on Smart City; IEEE 2nd International Conference on Data Science and Systems (HPCC/SmartCity/DSS) |
Keywords | Field | DocType |
Flash-based main memory system,TBuffer,History-aware identification,LazyFlush | Flash memory,Flash file system,Computer science,Cache,Parallel computing,Universal memory,Static random-access memory,Real-time computing,Memory rank,Memory controller,CAS latency | Conference |
ISBN | Citations | PageRank |
978-1-5090-4298-2 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhengguo Chen | 1 | 1 | 2.38 |
| Nong Xiao | 2 | 649 | 116.15 |
| Fang Liu | 3 | 1188 | 125.46 |
| Zhi-Guang Chen | 4 | 12 | 4.35 |
| Wei Chen | 5 | 86 | 12.45 |
| Yuxuan Xing | 6 | 5 | 1.78 |