Name
Abstract | ||
|---|---|---|
RISC-V is an open-source instruction set-architecture, designed to support customized extensions and architectures. This paper presents an instruction-set extension to the RISC-V ISA, idealized for software-defined radio applications. The custom instructions perform complex-number arithmetic, tailored for complex or quadrature modulation and baseband processing, and can perform one complex multiply-accumulate per cycle. The proposed system architecture includes the processor core, a WISHBONE bus interconnection, IO and peripherals, and was targeted to an Altera Cyclone III FPGA, achieving 0.9 DMIPS/MHz without the use of any compiler optimizations. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ASAP.2016.7760808 | 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP) |
Keywords | Field | DocType |
SDR,ASIP,DSP,RISC-V,Software-defined Radio,Baseband processor | RISC-V,Baseband,Wishbone,Computer science,Software-defined radio,Parallel computing,Field-programmable gate array,Baseband processor,Optimizing compiler,Multi-core processor,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-5090-1504-7 | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cecil Accetti R. de A. Melo | 1 | 1 | 0.69 |
| Edna Barros | 2 | 21 | 4.99 |