Name
Abstract | ||
|---|---|---|
This paper describes how the latest CakeML compiler supports verified compilation down to multiple realistically modelled target architectures. In particular, we describe how the compiler definition, the various language semantics, and the correctness proofs were organised to minimize target-specific overhead. With our setup we have incorporated compilation to four 64-bit architectures, ARMv8, x86-64, MIPS-64, RISC-V, and one 32-bit architecture, ARMv6. Our correctness theorem allows interference from the environment: the top-level correctness statement takes into account execution of foreign code and per-instruction interference from external processes, such as interrupt handlers in operating systems. The entire CakeML development is formalised in the HOL4 theorem prover. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3018610.3018621 | CPP |
Keywords | Field | DocType |
Compiler verification, ML, verified assembly | Interrupt,Dynamic compilation,Programming language,Computer science,Correctness,Compiler correctness,Parallel computing,Automated theorem proving,Compiler,Theoretical computer science,Machine code,Interference (wave propagation) | Conference |
Citations | PageRank | References |
3 | 0.39 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anthony C. J. Fox | 1 | 175 | 10.70 |
| Magnus O. Myreen | 2 | 621 | 35.67 |
| Yong Kiam Tan | 3 | 107 | 12.93 |
| Ramana Kumar | 4 | 141 | 13.56 |