Paper Info
Title
Eager Stack Cache Memory Transfers.
Abstract
The growing complexity of modern computer architectures increasingly complicates the prediction of the run-time behavior of software. For real-time systems, where a safe estimation of the programu0027s worst-case execution time is needed, time-predictable computer architectures promise to resolve this problem. The stack cache, for instance, allows the compiler to efficiently cache a programu0027s stack, while static analysis of its behavior remains easy.This work introduces an optimization of the stack cache that allows to anticipate memory transfers that might be initiated by future stack cache control instructions. These eager memory transfers thus allow to reduce the average-case latency of those control instructions, very similar to prefetching techniques known from conventional caches. However, the mechanism proposed here is guaranteed to have no impact on the worst-case execution time estimates computed by static analysis. Measurements on a dual-core platform using the Patmos processor and imedivision-multiplexing-based memory arbitration, show that our technique can eliminate up to 62% (7%) of the memory transfers from (respectively to) the stack cache on average over all programs of the MiBench benchmark suite.
Year
Venue
Field
2016
WCET
Cache pollution,Cache,Computer science,CPU cache,Parallel computing,Cache-only memory architecture,Page cache,Cache algorithms,Real-time computing,Stack trace,Cache coloring
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Amine Naji100.34
Florian Brandner220214.97