Title
An Efficient Channel Model for Evaluating Wireless NoC Architectures
Abstract
Wireless Networks-on-Chip (WiNoCs) have emerged to solve the scalability and performance bottleneck of conventional wired NoC architectures. However unlike communication in the macro-world, on-chip communication poses several constraints, hence there is the need for simulation and design tools that consider the effect of the wireless channel at the nanotechnology level. In this paper, we present a parameterizable channel model for WiNoCs which takes into account practical issues and constraints of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the on-chip antennas. The proposed channel model demonstrates that total path loss of the wireless channel in WiNoCs suffers from not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) which reduces the reliability of the system.
Year
DOI
Venue
2016
10.1109/SBAC-PADW.2016.23
2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)
Keywords
Field
DocType
Networks-on-Chip,WiNoC,Channel Model,MMA,Reliability,Wireless NoC
Bottleneck,System on a chip,Wireless,Computer science,Parallel computing,Communication channel,Path loss,Attenuation,Wi-Fi array,Scalability
Conference
ISBN
Citations 
PageRank 
978-1-5090-4845-8
0
0.34
References 
Authors
8
5
Name
Order
Citations
PageRank
Michael Opoku Agyeman17112.80
Quoc-Tuan Vien213626.06
Gary Hill300.34
Scott Turner463.96
Terrence S. T. Mak519833.28