Paper Info
Title
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks.
Abstract
The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs, power and ground (P/G) pins can account for the majority of the pins. This is because packages include separate pins for the disjoint processor and memory power delivery networks (PDNs). Supporting separate PDNs and P/G pins for processor and memory is inefficient, as each set has to be provisioned for the worst-case power delivery requirements. In this paper, we propose to reduce the number of P/G pins of both processor and memory in a 3D design, and dynamically and opportunistically divert some power between the two PDNs on demand. To perform the power transfer, we use a small bidirectional on-chip voltage regulator that connects the two PDNs. Our concept, called Snatch, is effective. It allows the computer to execute code sections with high processor or memory power requirements without having to throttle performance. We evaluate Snatch with simulations of an 8-core multicore stacked with two memory dies. In a set of compute-intensive codes, the processor snatches memory power for 30% of the time on average, speeding-up the codes by up to 23% over advanced turbo-boosting; in memory-intensive codes, the memory snatches processor power. Alternatively, Snatch can reduce the package cost by about 30%.
Year
DOI
Venue
2016
10.5555/3195638.3195704
MICRO-49: The 49th Annual IEEE/ACM International Symposium on Microarchitecture Taipei Taiwan October, 2016
Keywords
Field
DocType
Snatch,3D stacks,processor-memory power allocation,chip package,pin count,3D processor-memory designs,power ground pins,P-G pins,power delivery networks,PDN,bidirectional on-chip voltage regulator,memory power requirements,processor power requirements,8-core multicore simulations,memory dies,compute-intensive codes,turbo-boosting,memory-intensive codes
Disjoint sets,Computer science,Parallel computing,Provisioning,Finite-state machine,Chip,Real-time computing,Maximum power transfer theorem,Multi-core processor,Throttle,Voltage regulator,Embedded system
Conference
ISSN
ISBN
Citations 
1072-4451
978-1-4503-4952-9
1
PageRank 
References 
Authors
0.35
0
9
Name
Order
Citations
PageRank
Dimitrios Skarlatos132.40
Renji Thomas2713.44
Aditya Agrawal354634.80
Shibin Qin410.35
Robert C. N. Pilawa-Podgurski5245.75
Ulya R. Karpuzcu627722.27
Radu Teodorescu735623.38
Nam Sung Kim83268225.99
Josep Torrellas93838262.89