Name
Title | ||
|---|---|---|
Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation. |
Abstract | ||
|---|---|---|
Cache capacity and memory bandwidth play critical roles in application performance, particularly for data-intensive applications from domains that include machine learning, numerical analysis, and data mining. Many of these applications are also tolerant to imprecise inputs and have loose constraints on the quality of output, making them ideal candidates for approximate computing. This paper introduces a novel approximate computing technique that decouples the format of data in the memory hierarchy from the format of data in the compute subsystem to significantly reduce the cost of storing and moving bits throughout the memory hierarchy and improve application performance. This asymmetric compute-memory extension to conventional architectures, ACME, adds two new instruction classes to the ISA - load-concise and store-concise - along with three small functional units to the micro-architecture to support these instructions. ACME does not affect exact execution of applications and comes into play only when concise memory operations are used. Through detailed experimentation we find that ACME is very effective at trading result accuracy for improved application performance. Our results show that ACME achieves a 1.3X speedup (up to 1.8X) while maintaining 99% accuracy, or a 1.1X speedup while maintaining 99.999% accuracy. Moreover, our approach incurs negligible area and power overheads, adding just 0.005% area and 0.1% power to a conventional modern architecture.
|
Year | DOI | Venue |
|---|---|---|
2016 | 10.5555/3195638.3195688 | MICRO-49: The 49th Annual IEEE/ACM International Symposium on Microarchitecture
Taipei
Taiwan
October, 2016 |
Keywords | Field | DocType |
asymmetric compute-memory architecture,cache capacity,memory bandwidth,machine learning,numerical analysis,data mining,approximate computing technique,ACME | Memory hierarchy,Memory bandwidth,Address space layout randomization,Computer science,Parallel computing,Timing attack,Real-time computing,Side channel attack,Memory architecture,Speedup,Information and Computer Science | Conference |
ISSN | ISBN | Citations |
1072-4451 | 978-1-4503-4952-9 | 4 |
PageRank | References | Authors |
0.39 | 19 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Animesh Jain | 1 | 20 | 1.98 |
| Parker Hill | 2 | 39 | 2.70 |
| Shih-Chieh Lin | 3 | 33 | 2.17 |
| Muneeb Khan | 4 | 16 | 1.24 |
| Md E. Haque | 5 | 31 | 1.81 |
| Michael A. Laurenzano | 6 | 467 | 21.23 |
| Scott Mahlke | 7 | 4811 | 312.08 |
| Lingjia Tang | 8 | 1229 | 46.41 |
| Jason Mars | 9 | 1328 | 49.94 |