Name
Abstract | ||
|---|---|---|
with the increasing complexity of system on chip designs, the possibility of introducing changes after production becomes interesting. Therefore the integration of an embedded FPGA (eFPGA) in a System on Chip (SoC) allows the reuse of a portion of the chip. In the WSN nodes, dimensions of the chip should be as small as possible to optimize several constraints such as power consumption, run time and the price. In this paper we propose to introduce a reconfigurable coprocessor which is able to be reconfigurable at a specific time with a specific algorithm instead of using a standalone coprocessor for each one. Indeed, we present software / hardware interface to include a reconfigurable part in a Cortex-M0-based SoC. The software part describes the way to configure and to use the e-FPGA. The hardware interface allows handling the communication between the e-FPGA and the AHB bus. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/IDT.2016.7843061 | 2016 11th International Design & Test Symposium (IDT) |
Keywords | Field | DocType |
eFPGA,SoC,ARM,WSN,reconfigurable | System on a chip,Computer science,Reuse,Field-programmable gate array,Chip,Real-time computing,Software,Coprocessor,Wireless sensor network,Power consumption,Embedded system | Conference |
ISSN | ISBN | Citations |
2162-061X | 978-1-5090-4901-1 | 0 |
PageRank | References | Authors |
0.34 | 4 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hajer Saidi | 1 | 0 | 0.68 |
| Mariem Turki | 2 | 13 | 4.00 |
| Zied Marrakchi | 3 | 152 | 28.68 |
| Mohammed S. BenSaleh | 4 | 11 | 7.84 |
| Abid Mohamed | 5 | 39 | 19.08 |