Paper Info
Title
Multiprocessor architecture for an optimazed parallel model of covariance based person detection
Abstract
The covariance region descriptor has been proved robust in person detection application. However, detection is difficult to achieve on a serial processor. This is due to the large data set required to represent the image and the complex operations that need to be performed on the image. Multiprocessor systems (MPSoC) are usually adopted to speed up such application. In this paper, we propose a novel MPSoC architecture for fast person detection based on covariance descriptor. For this end, an optimized Khan Process Network parallel model of a covariance person detection application and the Sesame design and space exploration framework are used. Based on the optimal parallel model of covariance based person detection application, a multiprocessor architecture model is first proposed. These two models are modeled and validated using Sesame simulation. After that, the mapping of application tasks and channels on the architecture components is explored to define the optimal mapping architecture using execution time and platform cost. Results show that the six processors based architecture is the best when looking for the low computation cost and the four processors based architecture is the best when looking for the low cost.
Year
DOI
Venue
2016
10.1109/IDT.2016.7843017
2016 11th International Design & Test Symposium (IDT)
Keywords
Field
DocType
Covariance descriptor,person detection,MPSOC,optimized parallel model,Sesame
Architecture,Computer science,Communication channel,Multiprocessing,Real-time computing,Space exploration,MPSoC,Covariance,Computation,Speedup
Conference
ISSN
ISBN
Citations 
2162-061X
978-1-5090-4901-1
0
PageRank 
References 
Authors
0.34
6
5
Name
Order
Citations
PageRank
Abid, N.121.79
Tarek Ouni284.21
Kais Loukil354.86
Abid Mohamed43919.08
Ammeri, A.C.510.72