Name
Abstract | ||
|---|---|---|
Many VLSI-SoC include both, protection against soft errors and Built-In-Self-Test (BIST). This work investigates on the combination of both domains. The proposed approach offers additional functionality for BIST, i.e. self-test capabilities for the test logic itself and fault localization. A snapshot mode is offered as well. It enables the taking of snapshots of the current system state concurrently to task execution. The new approach was implemented and verified in various test circuits. The resource overhead is approx. 15 % in registers and 37 % in LUTs when synthesized for a FPGA, as compared to simple superposition of the initial approaches. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/VLSI-SoC.2016.7753569 | 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | Field | DocType |
integrated soft error resilience,very large scale integration,system-on-chip,VLSI-SoC,built-in-self-test,BIST,test logic,fault localization,snapshot mode,test circuits,resource overhead | Psychological resilience,Superposition principle,Soft error,Approx,Field-programmable gate array,Engineering,Electronic circuit,Snapshot (computer storage),Built-in self-test,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-5090-3562-5 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Erol Koser | 1 | 0 | 0.68 |
| Sebastian Krosche | 2 | 0 | 0.34 |
| Walter Stechele | 3 | 365 | 52.77 |