Abstract | ||
---|---|---|
In this paper, we propose a task allocation method for multi-core systems with the Duplication with Temporary Triple Modular Redundancy and Reconfiguration (DTTR) scheme. The proposed method optimizes both performance and reliability by allocating copies of tasks (i.e., redundant tasks) based on the maximum parallelism of tasks in a give application. In the experimental results, we compare the average failure rate of task allocations obtained by the proposed method with the one obtained by a scheduling-based task allocation method and the one obtained by a task allocation method based on Simulated Annealing. The proposed method realizes both high performance and high reliability in the cases when enough cores to maximize parallel execution of tasks exist. |
Year | DOI | Venue |
---|---|---|
2016 | 10.1109/MCSoC.2016.31 | 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) |
Keywords | Field | DocType |
Multi-core systems,task allocation,reliability,clique partitioning | Simulated annealing,Scheduling (computing),Computer science,Task parallelism,Parallel computing,Triple modular redundancy,Failure rate,Redundancy (engineering),Multi-core processor,Control reconfiguration | Conference |
ISBN | Citations | PageRank |
978-1-5090-3532-8 | 0 | 0.34 |
References | Authors | |
0 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Hiroshi Saito | 1 | 25 | 3.37 |
Masashi Imai | 2 | 1 | 2.07 |
Tomohiro Yoneda | 3 | 353 | 41.62 |