Name
Abstract | ||
|---|---|---|
IC functional failure is always a challenge for failure analysis engineers since it needs test pattern to access the defect location and electrically trigger it. Dynamic failure analysis is the only way to be used to do this kind of analysis. But it's time consuming and complex to employ dynamic analysis, so the success rate is lower and cycle time is longer. Static failure analysis is impossible to apply on these kinds of analysis since the test pattern and design information is needed. However, in this paper, the application of advanced FIB circuit edit (CE) was employed to isolate the suspected function block, and make it accessible to the DC bias. With static FA analysis, the defect location was successfully localized. Nanoprobing was employed on the further electrical analysis, and abnormal electrical performance was successfully observed. Combined with the device physics analysis, the suspected process was identified. Further PFA Wright etch was applied to visualize the defect which was a soft failure of Bipolar Junction Transistor (BJT) device. Failure mechanism was built up to explain the electrical and physical phenomena successfully. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1016/j.mejo.2017.01.013 | Microelectronics Journal |
Keywords | Field | DocType |
Circuit edit,Bipolar transistor,Implantation,Nanoprobing,Wright etch | Nanoprobing,Design information,Electrical performance,Electrical analysis,Wright etch,Electronic engineering,DC bias,Bipolar junction transistor,Electronic circuit,Physics | Journal |
Volume | Issue | ISSN |
62 | C | 0026-2692 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Q. Chen | 1 | 0 | 2.37 |
| G. B. Ang | 2 | 0 | 0.34 |
| Jeffrey Lam | 3 | 1 | 1.64 |
| Z. H. Mai | 4 | 1 | 4.34 |