Paper Info
Title
Cache Coherence Scheme for HCS-Based CMP and Its System Reliability Analysis.
Abstract
In previous work, a new network switch architecture, hybrid circuit-switched (HCS) network, has been proposed and evaluated. In doing so, it has been studied for use in a multi-processor system, with a focus on power and throughput. However, cache coherence and its connection with chip reliability have not been fully studied previously for multi-processor systems. In this paper, we study this problem by discussing the implementation of cache coherence on a HCS-based chip multi-processor and present a way to model the reliability of these protocols based on fault tree analysis and two-terminal networking models. We focus our efforts on three cache coherence protocols: Write-Once, Modified, Exclusive, Shared, Invalid (MESI), and Modified, Owned, Exclusive, Shared, Invalid (MOESI), and obtain expressions for the reliability probabilities of the system. Our results show that the Write-Once protocol is 14% less reliable than MOESI, while the MESI protocol is 2.5% less reliable than MOESI. We also demonstrate that the reliability of these protocols are 40.22% and 59.83% better, on average, when implemented on an HCS network rather than an elastic buffer-based network or a bus-based network, respectively.
Year
DOI
Venue
2017
10.1109/ACCESS.2017.2701406
IEEE ACCESS
Keywords
Field
DocType
Cache coherence,networking switch,system reliability,fault tree analysis (FTA),2-terminal model
MSI protocol,MOESI protocol,Computer science,MESIF protocol,MESI protocol,Computer network,Network switch,Memory coherence,Write-once,Distributed computing,Cache coherence
Journal
Volume
ISSN
Citations 
5
2169-3536
0
PageRank 
References 
Authors
0.34
21
2
Name
Order
Citations
PageRank
Sizhao Li132.40
Donghui Guo210721.93