Paper Info
Title
Design And Fpga Implementation Of A Universal Chaotic Signal Generator Based On The Verilog Hdl Fixed-Point Algorithm And State Machine Control
Abstract
In this paper, a novel design methodology and its FPGA hardware implementation for a universal chaotic signal generator is proposed via the Verilog HDL fixed-point algorithm and state machine control. According to continuous-time or discrete-time chaotic equations, a Verilog HDL fixed-point algorithm and its corresponding digital system are first designed. In the FPGA hardware platform, each operation step of Verilog HDL fixed-point algorithm is then controlled by a state machine. The generality of this method is that, for any given chaotic equation, it can be decomposed into four basic operation procedures, i.e. nonlinear function calculation, iterative sequence operation, iterative values right shifting and ceiling, and chaotic iterative sequences output, each of which corresponds to only a state via state machine control. Compared with the Verilog HDL floating-point algorithm, the Verilog HDL fixed-point algorithm can save the FPGA hardware resources and improve the operation efficiency. FPGA-based hardware experimental results validate the feasibility and reliability of the proposed approach.
Year
DOI
Venue
2017
10.1142/S0218127417500407
INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS
Keywords
Field
DocType
Chaotic system, fixed-point algorithm, state machine control, Verilog HDL, FPGA implementation
Nonlinear system,Computer science,Control theory,Parallel computing,Signal generator,Field-programmable gate array,Fixed point algorithm,Finite-state machine,Design methods,Verilog,Computer hardware,Chaotic
Journal
Volume
Issue
ISSN
27
3
0218-1274
Citations 
PageRank 
References 
2
0.40
4
Authors
6
Name
Order
Citations
PageRank
Mo Qiu120.40
Simin Yu232025.49
Yuqiong Wen320.40
Lv Jinhu42906244.29
Jian-Bin He5121.56
Zhuosheng Lin6263.27