Name
Title | ||
|---|---|---|
Decomposing Numerically Controlled Oscillator in Parallel Digital Down Conversion Architecture. |
Abstract | ||
|---|---|---|
The speed of digital signal processing device restricts the performance of the serial digital down conversion (DDC) architecture when the input of the DDC features a high sampling rate. As a result, the polyphase or parallel structure is adopted to relieve the speed pressure. This paper mainly studies the numerically controlled oscillator (NCO) decomposing in the parallel DDC structure, which can decompose the NCO's output into several branch signals which then can lower the operating speed of the mixer and the low pass filter (LPF) significantly, making it easier to implement DDC with field programmable gate array (FPGA). The mathematical expressions of the branch NCO outputs applied to the parallel DDC are deduced and the selection principles of the correlated parameters are discussed. The simulation and the experimental results of MATLAB show the corrections of the NCO decomposing technique. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1142/S0218126617501262 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
Digital down conversion,numerically controlled oscillator decomposing,parallel architecture,polyphase expression | Digital signal processing,Polyphase system,MATLAB,Numerically controlled oscillator,Control theory,Computer science,Operating speed,Sampling (signal processing),Field-programmable gate array,Electronic engineering,Low-pass filter | Journal |
Volume | Issue | ISSN |
26 | 9 | 0218-1266 |
Citations | PageRank | References |
1 | 0.37 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lianping Guo | 1 | 2 | 1.08 |
| Feng Tan | 2 | 1 | 0.37 |
| Peng Zhang | 3 | 1 | 0.37 |
| Hao Zeng | 4 | 8 | 4.60 |