Name
Abstract | ||
|---|---|---|
This paper presents a 200 kS/s 12-bit successive approximation ADC with a new ladder-based time-domain comparator. The proposed comparator utilizes differential multi-ladder stages, resulting in improvement of gain and noise performance. The chip is designed and fabricated in a standard 0.18 mu m CMOS technology with area of 0.127mm(2). With a supply of 0.9V, the ADC consumes 2.72 mu W at the sampling rate of 200 kS/s. The measured SNDR and SFDR are 61.6 dB and 66.1 dB respectively, providing an ENOB of 9.9 bits, and the corresponding FOM of 28 fJ/conv-step. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1587/elex.14.20170003 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
bio-medical devices, SAR ADC, time-domain comparator | Time domain,Comparator,Computer science,Electronic engineering,Successive approximation ADC | Journal |
Volume | Issue | ISSN |
14 | 5 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaolin Yang | 1 | 1 | 2.78 |
| Zhou Xiao | 2 | 84 | 19.21 |
| Lihan Tang | 3 | 0 | 1.69 |
| Yangtao Dong | 4 | 0 | 0.68 |
| Menglian Zhao | 5 | 16 | 6.31 |
| Lin Deng | 6 | 4 | 1.31 |
| Xiaobo Wu | 7 | 5 | 6.74 |
| Xiaolei Zhu | 8 | 88 | 13.07 |