Paper Info
Title
Fpga Implementation Of Highly Secure, Hardware-Efficient Qc-Ldpc Code-Based Nonlinear Cryptosystem For Wireless Sensor Networks
Abstract
This paper presents the design and implementation of an integrated architecture for embedding security into quasi-cyclic (QC) low-density parity-check (LDPC) code-based cryptographic system through a nonlinear function of low hardware complexity. Instead of using standard S-boxes for implementation of nonlinear function, this paper considers a method on the basis of maximum length cellular automata (CA), so that enhanced security can be achieved with simple hardware structure. The proposed system adopts a lightweight random bit stream generator on the basis of linear feedback shift register (LFSR) for generating random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with low hardware cost. Different permutation patterns generated for different message blocks help to provide good degrees of freedom for tuning security with reasonable key size. The hardware architecture for the proposed system is developed and validated through implementation on Xilinx Spartan 3S500E. Analytical and synthesis results show that the proposed scheme is lightweight and offers very high security through continuously changing parameters, thus making it highly suitable for resource-constrained applications.
Year
DOI
Venue
2017
10.1002/dac.3233
INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS
Keywords
Field
DocType
cellular automata, cryptosystem, ECBC, LFSR, QC-LDPC code
Computer science,Cryptography,Low-density parity-check code,Field-programmable gate array,Computer network,Cryptosystem,Real-time computing,Computer hardware,Bitstream,Wireless sensor network,Key size,Hardware architecture
Journal
Volume
Issue
ISSN
30
10
1074-5351
Citations 
PageRank 
References 
3
0.40
11
Authors
2
Name
Order
Citations
PageRank
Celine Mary Stuart161.81
P. P. Deepthi24010.40