Paper Info
Title
Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits.
Abstract
Radiation-induced soft errors have posed an increasing reliability challenge to combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise fast, accurate and scalable soft error rate (SER) estimation methods as part of cost-effective robust circuit design. This paper presents an efficient SER estimation framework for combinational and sequential circuits, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential elements. A novel top-down memoization algorithm is proposed to accelerate the propagation of SETs, and a general schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. The feedback in sequential logic is analyzed with an efficient time frame expansion method. Experimental results on various ISCAS85 combinational benchmark circuits demonstrate that the proposed approach achieves up to 560.2X times speedup with less than 3% difference in terms of SER results compared with the baseline algorithm. The average runtime of the proposed framework on a variety of ISCAS89 benchmark circuits is 7.20s, and the runtime is 119.23s for the largest benchmark circuit with more than 3,000 flip-flops and 17,000 gates.
Year
DOI
Venue
2017
10.1145/3035496
ACM Trans. Design Autom. Electr. Syst.
Keywords
Field
DocType
Soft error,single-event upset,multiple-cell upset,hardened flip-flop,algorithm
Sequential logic,Soft error,Computer science,Parallel computing,Circuit design,Combinational logic,Schematic,Real-time computing,CMOS,Memoization,Speedup
Journal
Volume
Issue
ISSN
22
3
1084-4309
Citations 
PageRank 
References 
4
0.43
19
Authors
2
Name
Order
Citations
PageRank
Ji Li19710.87
Jeff Draper229826.31