Name
Abstract | ||
|---|---|---|
This paper presents an ultralow power system on chip (SoC) for automatic sleep staging using a single electroencephalogram (EEG) channel. The system integrates an analog front end for EEG data acquisition and a digital processor to extract spectral features from these data and classify them into one of the sleep stages. The digital processor consists of multiple blocks implementing an automatic sl... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/JSSC.2017.2647923 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Sleep,Electroencephalography,Monitoring,Decision trees,Receivers,Signal processing algorithms,Algorithm design and analysis | Decision tree,Datapath,Computer science,Analog front-end,Electric power system,Communication channel,CMOS,Finite-state machine,Electronic engineering,Real-time computing,Sleep Stages | Journal |
Volume | Issue | ISSN |
52 | 3 | 0018-9200 |
Citations | PageRank | References |
2 | 0.39 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Syed Anas Imtiaz | 1 | 22 | 6.03 |
| Jiang Zhou | 2 | 41 | 13.69 |
| E Rodriguez-Villegas | 3 | 103 | 19.22 |