Title
A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology.
Abstract
This paper introduces a hybrid charge pump (HCP) architecture. The HCP enables high-voltage dc outputs in a nanometer-scale CMOS technology at improved power efficiency by optimally mixing different charge pump (CP) types that trade off voltage range and power efficiency. Conventional CP outputs in a bulk CMOS process are limited to a single-diode breakdown voltage (~12 V in a 65-nm technology nod...
Year
DOI
Venue
2017
10.1109/JSSC.2016.2636876
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Substrates,CMOS technology,Breakdown voltage,Switches,MOS devices,Switching circuits,Transistors
Electrical efficiency,Computer science,Voltage,Voltage doubler,Electronic engineering,CMOS,Breakdown voltage,Science, technology and society,Charge pump,Electrical engineering,Imagination
Journal
Volume
Issue
ISSN
52
3
0018-9200
Citations 
PageRank 
References 
7
0.76
10
Authors
4
Name
Order
Citations
PageRank
Yousr Ismail170.76
Haechang Lee27011.50
Sudhakar Pamarti336655.68
Chih-Kong Ken Yang4527128.86