Name
Abstract | ||
|---|---|---|
A dual-lane DC-to-12.5 Gb/s all-rate clock and data recovery (CDR) IC with a single LC voltage-controlled oscillator is fabricated in a 90 nm CMOS. An all-rate clock divider with an asynchronous phase calibration scheme is employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme that adjusts the bandwidth o... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/JSSC.2016.2646803 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Voltage-controlled oscillators,Frequency conversion,Jitter,Calibration,Bandwidth,Bit error rate | Clock signal,Clock gating,Frequency divider,Loop gain,Control theory,Computer science,Clock domain crossing,Electronic engineering,Voltage-controlled oscillator,CMOS,CPU multiplier | Journal |
Volume | Issue | ISSN |
52 | 3 | 0018-9200 |
Citations | PageRank | References |
1 | 0.43 | 18 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jong-Hyeok Yoon | 1 | 18 | 4.06 |
| soonwon kwon | 2 | 4 | 1.90 |
| Hyeon-min Bae | 3 | 91 | 20.77 |