Name
Abstract | ||
|---|---|---|
CGRAs are promising as accelerators due to their improved energy-efficiency compared to FPGAs. Existing CGRAs support reconfigurability for operations, but not communications because of the static neighbor-to-neighbor interconnect, leading to both performance loss and increased complexity of the compiler. In this paper, we introduce HyCUBE, a novel CGRA architecture with a reconfigurable interconnect providing single-cycle communications between distant FUs, resulting in a new formulation of the application mapping problem that leads to the design of an efficient compiler. HyCUBE achieves 1.5X and 3X better performance-per-watt compared to a CGRA with standard NoC and a CGRA with neighbor-to-neighbor connectivity, respectively. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3061639.3062262 | DAC |
Field | DocType | ISSN |
Kernel (linear algebra),Reconfigurability,Computer science,Efficient energy use,Field-programmable gate array,Electronic engineering,Compiler,Real-time computing,Schedule,Hop (networking),Interconnection,Embedded system | Conference | 0738-100X |
Citations | PageRank | References |
1 | 0.35 | 13 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manupa Karunaratne | 1 | 19 | 2.02 |
| Aditi Kulkarni Mohite | 2 | 3 | 1.39 |
| Tulika Mitra | 3 | 2714 | 135.99 |
| Li-Shiuan Peh | 4 | 2 | 1.04 |