Paper Info
Title
High-speed regular expression matching with pipelined automata
Abstract
Pattern matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links, pattern matching architectures have to be improved in order to retain wire-speed processing. Multi-striding is a well-known technique on how to increase throughput of pattern matching architectures. In the paper we provide an analysis of scalability of multi-striding and show that it does not scale well and cannot be used for 100Gbps throughput because utilization of FPGA resources grows exponentially. Therefore, we have designed a new hardware architecture for high-speed pattern matching that combines the multi-striding technique and parallel processing using pipelined finite state machines (FSMs). The architecture shares a single packet buffer for all parallel FSMs. Efficient implementation of the packet buffer reduces the number of BlockRAMs to 18% when compared to simple parallel implementation. Instead of multiplexing input data, the architecture pipelines the states of FSMs. Such pipelined processing with only local communication has a direct positive impact on frequency and throughput and allows us to scale the architecture to hundreds of Gbps.
Year
DOI
Venue
2016
10.1109/FPT.2016.7929431
2016 International Conference on Field-Programmable Technology (FPT)
Keywords
Field
DocType
high-speed regular expression matching,pipelined automata,network security monitoring,pattern matching architectures,multistriding,hardware architecture,parallel processing,pipelined finite state machines,FSMs,packet buffer,FPGA
Regular expression,Computer science,Parallel computing,Network packet,Finite-state machine,Real-time computing,Throughput,Multiplexing,Pattern matching,Hardware architecture,Scalability
Conference
ISBN
Citations 
PageRank 
978-1-5090-5603-3
0
0.34
References 
Authors
0
3
Name
Order
Citations
PageRank
Denis Matousek110.71
Jan Korenek29117.55
Viktor Pus3357.60