Name
Abstract | ||
|---|---|---|
This paper describes a CMOS 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) using TCC(Threshold Configuring Comparator) for the 5 MSBs. This architecture enables SAR to simplify C-DAC and reduce power consumption. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 750um × 700um. It consumes 53uW and achieves an ENOB of 9.7 bits at sampling frequency 10MS/s, power supply of 1.8V, and reference of 1.2 V. The Figure of Merit (FOM) is simulated to be 6.37fJ/step. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISOCC.2016.7799774 | 2016 International SoC Design Conference (ISOCC) |
Keywords | Field | DocType |
ADC,SAR,TCC,C-DAC | Capacitor,Comparator,Computer science,Sampling (signal processing),Analog-to-digital converter,Electronic engineering,Figure of merit,Effective number of bits,CMOS,Successive approximation ADC | Conference |
ISBN | Citations | PageRank |
978-1-5090-3220-4 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sang Heon Lee | 1 | 0 | 0.34 |
| Seong Jae Hyeon | 2 | 0 | 0.68 |
| Kim Jong Gu | 3 | 0 | 0.34 |
| Kwang-Sub Yoon | 4 | 0 | 2.37 |