Name
Abstract | ||
|---|---|---|
In this paper, we presents efficient hardware design of inter picture prediction in the slim high efficient video coding (HEVC). Compared with fully implemented HM10.0, our compression performance of inter prediction hardware block is decreased due to simplification. However our target is Real-time Encoder suitable for IoT, so our inter prediction block is small and fast. Also the verification of the inter prediction design is conducted using the ZYNQ and Virtex7. |
Year | Venue | Keywords |
|---|---|---|
2016 | 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | video coding, HEVC, inter prediction, VLSI, H.264/AVC |
Field | DocType | ISSN |
Computer science,Internet of Things,Coding (social sciences),Real-time computing,Encoder,Very-large-scale integration | Conference | 2163-9612 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaehyuk So | 1 | 0 | 0.34 |
| Junwon Mun | 2 | 0 | 0.34 |
| Kyungmook Oh | 3 | 1 | 1.36 |
| Jaeseok Kim | 4 | 405 | 58.33 |