Title
A transient enhanced external capacitor-less LDO with a CMOS only sub-bandgap voltage reference
Abstract
This paper presents an external capacitor-less low-dropout(LDO) regulator with a voltage spike detection circuit for the enhanced transition response and with a CMOS only sub-bandgap voltage reference(BGR) operated in subthreshold region. CMOS sub-BGR adopted a weighted Vgs structure and a body bias technique for reducing the variations from process, voltage and temperature (PVT). The proposed LDO achieved the PSRR of -96dB at DC and -34dB at 1MHz by using 3-stage configuration. The proposed LDO operates with the reference voltage of 283mV from the Sub-BGR and provides the output voltage of 1.5V. Simulated results shows that overshoot and undershoot of output voltage were reduced to 62mV and 56mV respectively when the load current changes from 0 to 50mA. Total power consumption was 60μA and the chip area was 0.03358mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 0.18μm CMOS process.
Year
DOI
Venue
2016
10.1109/ISOCC.2016.7799772
2016 International SoC Design Conference (ISOCC)
Keywords
Field
DocType
Bandgap reference,sub-BGR,LDO,regulator
Computer science,Voltage reference,Overdrive voltage,Electronic engineering,Electrical engineering,Low-dropout regulator,Voltage regulator,Bandgap voltage reference,Voltage divider,Dropout voltage,Voltage droop
Conference
ISSN
ISBN
Citations 
2163-9612
978-1-5090-3220-4
0
PageRank 
References 
Authors
0.34
3
3
Name
Order
Citations
PageRank
Chang-Bum Park100.34
Chan-Kyeong Jung200.34
Shin-il Lim3810.10