Name
Title | ||
|---|---|---|
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC |
Abstract | ||
|---|---|---|
Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes the design and implementation of an asynchronous router architecture suitable for a network-on-chip in the context of a Vision-System-on-Chip. The developed design flow for the synthesis of asynchronous bundled-data pipelines is based on common synthesis tools and, therefore, enables high compatibility with synchronous designs and a low barrier to entry. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/DDECS.2017.7934579 | 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) |
Keywords | Field | DocType |
network-on-chip,low power,low latency,GALS,asynchronous circuits,vision-system-on-chip,CAD,synthesis | CAD,Asynchronous communication,Synchronization,Asynchronous system,Synchronizer,Computer science,Design flow,Real-time computing,Router,Routing protocol,Distributed computing | Conference |
ISSN | ISBN | Citations |
2334-3133 | 978-1-5386-0473-1 | 1 |
PageRank | References | Authors |
0.41 | 13 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Patrick Russell | 1 | 2 | 0.82 |
| Jens Döge | 2 | 10 | 4.17 |
| christoph hoppe | 3 | 6 | 2.32 |
| Thomas B. Preusser | 4 | 58 | 6.60 |
| peter reichel | 5 | 6 | 2.32 |
| Peter Schneider | 6 | 6 | 4.19 |