Name
Abstract | ||
|---|---|---|
Repeaterless low swing interconnects have been proposed for enhancing the performance of long on-chip interconnects. Synchronization of these high speed, low swing interconnects is important for proper operation. This paper discusses a clock synchronizing circuit for low swing interconnects. The circuit uses a combination of a delay locked loop (DLL), that generates multiple phases of the clock, and an analog voltage controlled delay line (VCDL). The circuit picks one of the phases of the DLL and tries to achieve lock by delaying this clock using the VCDL. If the VCDL range is not sufficient to achieve lock, a coarse correction is automatically triggered by the circuit, which is realized by picking the next adjacent phase of the DLL. Using the multiple clock phases inherently available in the system, a low latency clock domain transfer from the sampling clock domain to the receiver clock domain is achieved. The proposed synchronizer has been designed and fabricated in UMC 130 nm CMOS technology. The circuit consumes 1.4 mW from a 1.2 V supply at a data rate of 1.3 Gbps. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/VLSID.2017.12 | 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
Current mode interconnects,Low swing inter-connect,repeater insertion,clock data recovery,Mesochronous synchronizers | Clock gating,Underclocking,Computer science,Clock domain crossing,Real-time computing,Electronic engineering,Clock skew,Synchronous circuit,Digital clock manager,CPU multiplier,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-5090-5741-2 | 2 |
PageRank | References | Authors |
0.42 | 11 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naveen Kadayinti | 1 | 3 | 1.13 |
| Maryam Shojaei Baghini | 2 | 86 | 29.67 |
| Dinesh Kumar Sharma | 3 | 48 | 11.91 |