Name
Title | ||
|---|---|---|
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model |
Abstract | ||
|---|---|---|
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Automatic test pattern generation for open faults is challenging, because of their rather unstable behavior and the numerous electrical parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints like the influence of the aggressors on the open net and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy. Yet, this leads to the problem that not only generated tests may be invalidated but also the localization of a specific fault may fail - in case such a model is used as basis for diagnosis. Furthermore, most of the models do not consider the problem of oscillating behavior, caused by feedback introduced by coupling capacitances, which occurs in almost all designs. In [1], the Robust Enhanced Aggressor Victim Model (REAV) and in [2] an extension to address the problem of oscillating behavior were introduced. The resulting model does not only consider the influence of all aggressors accurately but also guarantees robustness against oscillating behavior as well as process variations affecting the thresholds of gates driven by an open interconnect. In this work we present the first diagnostic classification algorithm for this model. This algorithm considers all constraints enforced by the REAV model accurately - and hence handles unknown values as well as oscillating behavior. In addition, it allows to distinguish faults at the same interconnect and thus reducing the area that has to be considered for physical failure analysis. Experimental results show the high efficiency of the new method handling circuits with up to 500,000 non-equivalent faults and considerably increasing the diagnostic resolution. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/VLSID.2017.34 | 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
Interconnect opens,test generation,ATPG,unknown values,SMT,diagnose | Automatic test pattern generation,Logic gate,Coupling,Computer science,Diagnostic classification,Real-time computing,Robustness (computer science),Electronic engineering,Electronic circuit,Interconnection | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-5090-5741-2 | 1 |
PageRank | References | Authors |
0.35 | 20 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pascal Raiola | 1 | 3 | 2.77 |
| Dominik Erb | 2 | 33 | 4.45 |
| Sudhakar M. Reddy | 3 | 5747 | 699.51 |
| B. Becker | 4 | 191 | 21.44 |