Name
Abstract | ||
|---|---|---|
Reconfigurable cores support post-release updates which shortens time-to-market while extending circuits' lifespan. Reconfigurable cores can be provided as hard cores (ASIC) or soft cores (RTL). Soft reconfigurable cores outperform hard reconfigurable cores by preserving the ASIC synthesis flow, at the cost of lowering scalability but also exacerbating timing closure issues. This article tackles these two issues and introduces the ARGen generator that produces scalable soft reconfigurable cores. The architectural template relies on injecting flip-flops into the interconnect, to favor easy and accurate timing estimation. The cores are compliant with the academic standard for place and route environment, making ARGen a one stop shopping point for whoever needs exploitable soft reconfigurable cores. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1007/978-3-319-56258-2_9 | Lecture Notes in Computer Science |
Field | DocType | Volume |
Computer science,Parallel computing,Place and route,Application-specific integrated circuit,Real-time computing,Electronic circuit,Interconnection,Timing closure,Programmable logic device,Scalability,Embedded system | Conference | 10216 |
ISSN | Citations | PageRank |
0302-9743 | 1 | 0.35 |
References | Authors | |
5 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Theotime Bollengier | 1 | 5 | 1.16 |
| Loïc Lagadec | 2 | 62 | 12.84 |
| Najem, M. | 3 | 12 | 3.73 |
| Jean-christophe Le Lann | 4 | 84 | 7.49 |
| Pierre Guilloux | 5 | 1 | 0.35 |