Name
Abstract | ||
|---|---|---|
Modern System-on-Chip (SoC) designs face many challenges. Choosing the best communication protocol among the different processing nodes is one of the most important design decisions. On-chip communication architectures can have a significant impact on the performance of SoC designs. However, in most of the existing design tools, only the computation cost is accurately estimated. To address this challenge, we present a high-level analytical tool to estimate the data communication cost for hybrid CPU-FPGA architectures. The proposed model allows to estimate, rapidly and accurately, both computation and communication cost of applications containing multiple nested loops. This paper also explores the benefits of applying various optimization pragmas including dataflow and loop pipelining, at the compilation phase. Experimental results show that the proposed model provides accurate data communication estimation for hybrid CPUFPGA architectures. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/PDP.2017.11 | 2017 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP) |
Keywords | Field | DocType |
HLS,FPGA,SoC,Hardware accelerator | Computer architecture,Computer science,Loop pipelining,Parallel computing,Field-programmable gate array,Dataflow,Hardware acceleration,Communications protocol,Nested loop join,Computation | Conference |
ISSN | ISBN | Citations |
1066-6192 | 978-1-5090-6059-7 | 1 |
PageRank | References | Authors |
0.35 | 9 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mariem Makni | 1 | 3 | 2.08 |
| Smaïl Niar | 2 | 75 | 23.58 |
| Mouna Baklouti | 3 | 36 | 10.24 |
| Guanwen Zhong | 4 | 39 | 3.43 |
| Tulika Mitra | 5 | 2714 | 135.99 |
| Mohamed Abid | 6 | 171 | 29.34 |