Title
Exploiting latency variation for access conflict reduction of NAND flash memory
Abstract
NAND flash memory has been widely used in storage systems by offering greater read/write performance and lower power consumption than mechanical hard drives. Recently, the tradeoff between endurance, write speed, and read speed has been exploited from many ways for I/O performance improvement, which also induce the read/write latency variation. In this paper, the latency variation is exploited in I/O scheduling for access characteristic guided read and write latency minimization. First, with the understanding of the relationship among read latency, write latency and raw bit error rates (RBER), different ways to exploit the relationship for read and write latency reduction is discussed. Then, an I/O scheduling scheme is proposed by using hotness and retention age of accessed data to determine the speed of writes or reads, giving scheduling priority to fast writes and fast reads for conflict reduction. Experiments with various traces reveal that the proposed technique achieves significant read and write performance improvements.
Year
DOI
Venue
2016
10.1109/MSST.2016.7897088
2016 32nd Symposium on Mass Storage Systems and Technologies (MSST)
Keywords
Field
DocType
latency variation,access conflict reduction,NAND flash memory,storage systems,power consumption,mechanical hard drives,IO performance improvement,read-write latency variation,access characteristic guided read-and-write latency minimization,raw bit error rates,RBER,IO scheduling scheme,retention age,scheduling priority
Nand flash memory,Scheduling (computing),Latency (engineering),Computer science,Exploit,Minification,Memory management,Computer hardware,Performance improvement,Power consumption
Conference
ISSN
ISBN
Citations 
2160-195X
978-1-4673-9056-9
0
PageRank 
References 
Authors
0.34
9
5
Name
Order
Citations
PageRank
Jinhua Cui1264.63
Weiguo Wu214834.44
Xingjun Zhang38134.06
Jianhang Huang4136.37
Yinfeng Wang56113.10