Paper Info
Title
REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance
Abstract
Continuous technology scaling makes NAND flash cells much denser. As a result, NAND flash is becoming more prone to various interference errors. Due to the hardware circuit design mechanisms of NAND flash, retention errors have been recognized as the most dominant errors, which affect the data reliability and flash lifetime. Furthermore, after experiencing a large number of programm/erase (P/E) cycles, flash memory would suffer a much higher error rate, rendering traditional ECC codes (typically BCH codes) insufficient to ensure data reliability. Therefore, low density parity check (LDPC) codes with stronger error correction capability are used in NAND flash-based storage devices. However, directly using LDPC codes with belief propagation (BP) decoding algorithm introduces non-trivial overhead of decoding latency and hence significantly degrades the read performance of NAND flash. It has been observed that flash retention errors show the so-called numerical-correlation characteristic (i.e., the 0-1 bits stored in the flash cell affect each other with the leakage of the charge) in each flash cell. In this paper, motivated by the observed characteristic, we propose REAL: a retention error aware LDPC decoding scheme to improve NAND flash read performance. The developed REAL scheme incorporates the numerical-correlation characteristic of retention errors into the process of LDPC decoding, and leverages the characteristic as additional bits decision information to improve its error correction capabilities and decrease the decoding latency. Our simulation results show that the proposed REAL scheme can reduce the LDPC decoding latency by 26.44% and 33.05%, compared with the Logarithm Domain Min-Sum (LD-MS) and Probability Domain BP (PD-BP) schemes, respectively.
Year
DOI
Venue
2016
10.1109/MSST.2016.7897085
2016 32nd Symposium on Mass Storage Systems and Technologies (MSST)
Keywords
Field
DocType
decoding latency,error correction capability improvement,bit decision information,flash cell,numerical-correlation characteristic,BP decoding algorithm,propagation decoding algorithm,error correction capability,low-density parity check codes,P/E cycles,programm/erase cycles,flash lifetime,data reliability,hardware circuit design mechanisms,NAND flash read performance improvement,retention error aware LDPC decoding scheme,REAL
Sequential decoding,Flash memory,Computer science,Low-density parity-check code,Serial concatenated convolutional codes,Parallel computing,NAND gate,Error detection and correction,Decoding methods,List decoding,Computer engineering
Conference
ISSN
ISBN
Citations 
2160-195X
978-1-4673-9056-9
4
PageRank 
References 
Authors
0.48
25
6
Name
Order
Citations
PageRank
Meng Zhang1165.23
Fei Wu210435.76
Xubin He374763.49
Ping Huang418429.52
Shunzhuo Wang5122.30
Changsheng Xie636666.54