Name
Abstract | ||
|---|---|---|
Multiple-valued logic (MVL) has potential advantages for energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuit designs. We design a novel ternary multiplier based on a ternary CMOS (T-CMOS) compact model. To estimate performance and energy efficiency of our ternary design, we construct a standard ternary-cell library and exploit a ternary static timing analysis (T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISMVL.2017.52 | 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) |
Keywords | Field | DocType |
MVL,Ternary multiplier,T-STA | Logic gate,Adder,Circuit complexity,Computer science,Multiplier (economics),Ternary operation,Electronic engineering,CMOS,Static timing analysis,Performance improvement | Conference |
ISBN | Citations | PageRank |
978-1-5090-5497-8 | 2 | 0.46 |
References | Authors | |
3 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yesung Kang | 1 | 3 | 1.82 |
| Jaewoo Kim | 2 | 2 | 0.80 |
| Sunmin Kim | 3 | 4 | 2.22 |
| Sunhae Shin | 4 | 4 | 0.87 |
| E-San Jang | 5 | 2 | 0.46 |
| Jae Won Jeong | 6 | 4 | 0.87 |
| Kyung Rok Kim | 7 | 6 | 2.33 |
| Seokhyeong Kang | 8 | 388 | 32.89 |