Name
Abstract | ||
|---|---|---|
Voltage scaling has been used as a prominent technique to improve energy efficiency in digital systems, scaling down supply voltage effects in quadratic reduction in energy consumption of the system. Reducing supply voltage induces timing errors in the system that are corrected through additional error detection and correction circuits. In this paper we are proposing voltage over-scaling based approximate operators for applications that can tolerate errors. We characterize the basic arithmetic operators using different operating triads (combination of supply voltage, body-biasing scheme and clock frequency) to generate models for approximate operators. Error-resilient applications can be mapped with the generated approximate operator models to achieve optimum trade-off between energy efficiency and error margin. Based on the dynamic speculation technique, best possible operating triad is chosen at runtime based on the user definable error tolerance margin of the application. In our experiments in 28nm FDSOI, we achieve maximum energy efficiency of 89% for basic operators like 8-bit and 16-bit adders at the cost of 20% Bit Error Rate (ratio of faulty bits over total bits) by operating them in near-threshold regime. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.23919/DATE.2017.7927036 | DATE |
Keywords | Field | DocType |
voltage over-scaling,error-resilient applications,energy efficiency improvement,digital systems,supply voltage effects,quadratic reduction,energy consumption,supply voltage reduction,timing errors,error correction circuits,error detection circuits,approximate operators,error tolerance,arithmetic operators,body-biasing scheme,clock frequency,error margin,dynamic speculation technique,error tolerance margin,FDSOI technology,adders,bit error rate,size 28 nm,word length 8 bit,word length 16 bit | Adder,Computer science,Efficient energy use,Real-time computing,Electronic engineering,Error detection and correction,Operator (computer programming),Energy consumption,Margin of error,Clock rate,Bit error rate | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-5090-5826-6 | 2 |
PageRank | References | Authors |
0.36 | 14 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| rengarajan ragavan | 1 | 5 | 1.09 |
| Benjamin Barrois | 2 | 8 | 1.54 |
| Cedric Killian | 3 | 14 | 5.04 |
| Olivier Sentieys | 4 | 597 | 73.35 |