Abstract | ||
---|---|---|
In recent years, the demand for memory performance has grown rapidly due to the increasing number of cores on a single CPU, along with the integration of graphics processing units and other accelerators. Caching has been a very effective way to relieve bandwidth demand and to reduce average memory latency. As shown by the cache feature table in Fig. 23.9.1, there is a big latency gap between SRAM caches in the CPU and the external DRAM main memory. As a key element for future computing systems, the last level cache (LLC) should have a high random access bandwidth, a low random access latency, a density of 1 to 8Gb, and all signal pads located on one side of the chip [1]. A logic-process-based solution was proposed [2], but it is not scalable, and has a high standby current due to its need for frequent refresh. HBM2 was also proposed [3], but its row latency is not better than conventional DRAM, and its random-access bandwidth is still limited by t FAW , as shown in Fig. 23.9.1. This paper describes the high-bandwidth low-latency (HBLL) RAM design: how it overcomes these challenges and meets requirements in a cost-effective way. |
Year | Venue | Field |
---|---|---|
2017 | ISSCC | Central processing unit,Tag RAM,Cache pollution,Computer science,Latency (engineering),Cache,Parallel computing,Static random-access memory,CAS latency,Embedded system,Random access |
DocType | Citations | PageRank |
Conference | 2 | 0.39 |
References | Authors | |
3 | 20 |
Name | Order | Citations | PageRank |
---|---|---|---|
Tah-Kang Joseph Ting | 1 | 2 | 0.39 |
Gyh-Bin Wang | 2 | 2 | 0.39 |
Ming-Hung Wang | 3 | 2 | 0.39 |
Chun-Peng Wu | 4 | 2 | 0.39 |
Chun-kai Wang | 5 | 44 | 4.67 |
Chun-Wei Lo | 6 | 2 | 0.39 |
Li-Chin Tien | 7 | 2 | 0.39 |
Der-Min Yuan | 8 | 2 | 0.39 |
Yung-Ching Hsieh | 9 | 2 | 0.39 |
Jenn-Shiang Lai | 10 | 3 | 1.78 |
Wen-Pin Hsu | 11 | 2 | 0.39 |
Chien-Chih Huang | 12 | 224 | 10.26 |
Chi-Kang Chen | 13 | 4 | 2.45 |
Yung-Fa Chou | 14 | 10 | 2.26 |
Ding-Ming Kwai | 15 | 521 | 46.85 |
Zhe Wang | 16 | 2 | 0.39 |
Wu Wei | 17 | 204 | 14.84 |
Shigeki Tomishima | 18 | 2 | 0.39 |
Patrick Stolt | 19 | 2 | 0.39 |
Shih-Lien Lu | 20 | 958 | 67.34 |