Name
Abstract | ||
|---|---|---|
Continued proliferation of semiconductors drives the evolution of nonvolatile memory technologies towards higher density, lower power consumption, and lower cost. This year, NAND Flash memories are demonstrated in 3D technologies with up to 64 stacked word-line layers. An embedded split-gate NOR Flash is also shown to dramatically reduce power consumption and meet the requirements of high-temperature sensing applications. Finally, logic anti-fuse one-time-programmable (OTP) memory is scaled down to the 10nm technology node. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISSCC.2017.7870327 | 2017 IEEE International Solid-State Circuits Conference (ISSCC) |
Field | DocType | ISBN |
Sensing applications,Non-volatile random-access memory,Computer science,NAND gate,Non-volatile memory,Computer memory,Electrical engineering,Charge trap flash,Power consumption,Embedded system | Conference | 978-1-5090-3759-9 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takashi Kono | 1 | 0 | 1.01 |
| Ki Tae Park | 2 | 24 | 6.23 |
| Leland Chang | 3 | 13 | 6.71 |