Abstract | ||
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High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash, recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015, and reached 48 layers in 2016. Also, density as high as 2.62 and 4.29Gb/mm
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were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: four-block even-odd-combined row decoding to effectively address the increase of stacked layers; unselected string pre-charge operation to improve endurance and reliability, and; shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features. |
Year | DOI | Venue |
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2017 | 10.1109/ISSCC.2017.7870328 | 2017 IEEE International Solid-State Circuits Conference (ISSCC) |
Keywords | Field | DocType |
64-word-line-layer BiCS technology,floating-gate,FG,lithography,2D-NAND flash memory,ISSCC,high-density multistacked 3D-flash memory,four-block even-odd-combined row decoding,reliability,shielded BL current sensing,storage capacity 512 Gbit,storage capacity 3 bit | Shielded cable,Logic gate,Coupling,Flash memory,Computer science,Electronic engineering,Lithography,Throughput,Decoding methods,Scaling,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-3759-9 | 2 | 0.38 |
References | Authors | |
5 | 57 |