Name
Title | ||
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10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response |
Abstract | ||
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Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage in such devices, stacked MOSFET structures with a three-level technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. A three-level single-inductor triple-output (SITO) converter was shown here and also compares the transient response with the SITO converter without the three-level technique. The three-level topology applies three different voltages, V
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1/2V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub>
and V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub>
, to the node V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub>
. The operation mode is determined by the duty cycle, i.e., the node V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub>
swings between 1/2V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub>
and V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub>
when duty cycle (D <; 0.5), and between 1/2V
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and V
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, otherwise (D>0.5). In state-of-the-art , the key issue of the three-level topology is how to balance the cross voltage of flying capacitor C
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FLY</sub>
at the point of 1/2V
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. In general, the restrained output voltage ripple and the flatter inductor current (I
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) slope seriously result in worse transient response and severe cross-regulation (CR) problems, respectively. Results show that the three-level SITO converter achieves a smaller output voltage ripple in steady state, but it causes the problems of slower transient response time, longer recovery time, larger overshoot/undershoot, and severe CR. Thus, it is desired to develop a technique that can adjust the cross voltage of C
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FLY</sub>
such that the three-level topology achieves higher efficiency, lower output voltage ripple, and fast transient response simultaneously. To resolve the aforementioned problems, this paper presents a three-level SITO converter, with the adjustable flying capacitor (AFC) technique, controlled by the superposition ramp control (SRC). The SRC controls on/off time of the power MOSFETs M1-M4 and the output switches SO1-SO3 synchronously where the cross voltage of CFLY is adjusted by the AFC in case of any load changes. Based on the output voltage variation, the CFLY controller of the AFC regulates the load-dependent cross voltage across the CFLY which increases the inductor current slope for fast transient response with a controllable closed loop. On the other hand, for the steady state, the CFLY controller adjusts the cross voltage to 1/2 V
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub>
to minimize the output voltage ripple and achieve high efficiency. Thus, the three-level topology reduces the output voltage ripple, the AFC technique not only speeds up the transient response but also reduces the CR. Measurement results show that the proposed converter achieves a peak efficiency of 89.6 % with output ripples within 3.5mV, and CR and load regulation are 0.028 (mV/mA) and 0.06 (mV/mA), respectively, with only 2.2μH inductor and 2μF output capacitors. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISSCC.2017.7870323 | 2017 IEEE International Solid-State Circuits Conference (ISSCC) |
Keywords | Field | DocType |
three level converter,single inductor converter,triple output converter,adjustable flying capacitor technique,low output ripple converter,fast transient response converter,restrained output voltage ripple,flatter inductor current,superposition ramp control,power MOSFET control,voltage regulation | Transient response,Boost converter,Capacitor,Computer science,Duty cycle,Control theory,Voltage,Inductor,Electronic engineering,CMOS,Ripple,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-3759-9 | 2 | 0.53 |
References | Authors | |
5 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Li-Cheng Chu | 1 | 2 | 1.21 |
| Wen-Hau Yang | 2 | 8 | 3.96 |
| Xiao-Qing Zhang | 3 | 2 | 0.53 |
| Yan-Jiun Lai | 4 | 5 | 1.26 |
| Ke-Horng Chen | 5 | 379 | 90.04 |
| Chin-Long Wey | 6 | 316 | 56.51 |
| Ying-Hsi Lin | 7 | 112 | 30.84 |
| Shian-Ru Lin | 8 | 13 | 8.38 |
| Tsung-Yen Tsai | 9 | 37 | 20.41 |