Paper Info
Title
A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications
Abstract
A restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning applications in this paper. Featuring neural network (NN) model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism in learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology, the proposed RBM-P chip costs 2.2M gates and 128kB SRAM with 8.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. Operated at 1.2V and 210MHz, this chip respectively achieves 114.3x and 3.9x faster processing time than CPU and GPGPU. And the proposed RBM-P chip consumes 41.3pJ and 26.7pJ per neuron weight (NW) for learning and inference, respectively.
Year
DOI
Venue
2016
10.1109/ASSCC.2016.7844186
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Keywords
Field
DocType
restricted Boltzmann machine (RBM),machine learning,non-linear functions,low power design
Restricted Boltzmann machine,Clock gating,Early stopping,Computer science,Static random-access memory,Chip,Real-time computing,Bandwidth (signal processing),Artificial neural network,Auxiliary memory
Conference
ISBN
Citations 
PageRank 
978-1-5090-3701-8
0
0.34
References 
Authors
4
4
Name
Order
Citations
PageRank
Chang-Hung Tsai192.43
Wan-Ju Yu221.14
Wing Hung Wong360796.45
Chen-Yi Lee41211152.40