Name
Title | ||
|---|---|---|
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASSCC.2011.6123627 | A-SSCC |
Keywords | Field | DocType |
chip,low power electronics,failure rate,system on a chip | System on a chip,Computer science,Process corners,Voltage,Chip,Static random-access memory,Electronic engineering,Real-time computing,Trimming,Low-power electronics,Memory cell | Conference |
Citations | PageRank | References |
1 | 0.39 | 2 |
Authors | ||
12 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keiichi Kushida | 1 | 71 | 10.19 |
| Osamu Hirabayashi | 2 | 1 | 0.39 |
| Fumihiko Tachibana | 3 | 37 | 5.98 |
| Hiroyuki Hara | 4 | 1 | 0.73 |
| Atsushi Kawasumi | 5 | 153 | 19.91 |
| atsushi suzuki | 6 | 1 | 0.39 |
| Yasutoyo Takeyama | 7 | 12 | 1.52 |
| yasuhiro fujimura | 8 | 42 | 5.59 |
| Yusuke Niki | 9 | 44 | 5.58 |
| Miyako Shizuno | 10 | 5 | 1.15 |
| Shin-ichi Sasaki | 11 | 160 | 44.66 |
| Tomoaki Yabe | 12 | 86 | 11.09 |