Paper Info
Title
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.
Abstract
Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technologies, power gating, and near- and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET circuits operating in near- and super-threshold voltage regimes for embedded system applications. A joint optimization algorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99.9% energy reductions when compared to the near-threshold approach without power gating and 95.3% when compared to deadline-free optimization.
Year
DOI
Venue
2017
10.1145/3060403.3060424
ACM Great Lakes Symposium on VLSI
Field
DocType
Citations 
Power saving,Computer science,Electronic engineering,Real-time computing,Optimization algorithm,Power consumption,Voltage,Power gating,Transistor,Electronic circuit,Electrical engineering,Operating voltage,Embedded system
Conference
0
PageRank 
References 
Authors
0.34
7
5
Name
Order
Citations
PageRank
Huimei Cheng142.44
Ji Li29710.87
Jeff Draper329826.31
Shahin Nazarian432738.55
Yanzhi Wang51082136.11