Name
Title | ||
|---|---|---|
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits. |
Abstract | ||
|---|---|---|
This paper proposes a low-power non-volatile programmable inverter cell (NVPINV) that can be used with a COGRE (i.e. a compactly organized generic reconfigurable element) circuit to store the correct information for programming when establishing the desired logic function. The programmable data in the cell is read from a non-volatile SRAM (NVSRAM); two RMs (racetrack memories) are utilized as non-volatile elements. The RM is selected as non-volatile memory element due to its capability for independent operations (read and write), thus making possible a parallel execution of the programming process. The NVSRAM operates as a programmable circuit, i.e. a programmable circuit under control as either a buffer, or an inverter. The cell is extensively analyzed in terms of its operations with respect to different figures of merit, such as delay, power dissipation and power delay product (PDP). Simulation results show that in addition to low-power operation, the proposed NVPINV cell provides significant advantages (such as low delay and non-volatile storage) compared to an SRAM based Look-Up-Table (LUT) implementation. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3060403.3060405 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
Non-volatile memory, Racetrack Memory, FPGA, Programmable inverter, Emerging Technology | Inverter,nvSRAM,Power–delay product,Computer science,Programmable logic array,Simple programmable logic device,Field-programmable gate array,Electronic engineering,Computer hardware,Electronic circuit,Racetrack memory | Conference |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pilin Junsangsri | 1 | 28 | 5.78 |
| Fabrizio Lombardi | 2 | 57 | 10.81 |
| Salin Junsangsri | 3 | 0 | 0.34 |
| Martin Margala | 4 | 75 | 9.77 |